View 79RC32364_311488.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

RISControllerTM Embedded 32-bit Microprocessor, based on RISCore32300
79RC32364TM
Features
High-performance embedded RISController microprocessor, based on IDT RISCore32300TM 32-bit CPU core - Based on MIPS 32 RISC architecture with enhancements - Scalar 5-stage pipeline minimizes branch and load delays - 66 Million multiply accumulate (MAC) Mul-Add/second @ 133MHz - 100 and 133 frequencies x MIPS 32 (ISA) instruction set architecture - MIPS IV compatible conditional move instructions - MIPS IV superset PREF (prefetch) instruction - Fast multiplier with atomic multiply-add, multiply-sub - Count leading zeros/ones instructions x Large, efficient on-chip caches - Separate 8kB Instruction cache and 2kB Data cache - 2-way set associative - Write-back and write-through support on a per page basis - Optional cache locking with "per line" resolution, to facilitate deterministic response - Simultaneous instruction and data fetch in each clock cycle, sustained rate, achieves over 1 GB/sec bandwidth
x TM
Flexible RC4000 compatible MMU with 32-page TLB on-chip - Variable page size - Variable number of locked entries - No performance penalty for address translation x Flexible bus interface allows simple, low-cost designs - Bus interface runs at a fraction of pipeline rate - Programmable port-width interface (8-,16-, 32-bit memory and I/O regions) - Programmable bus turnaround times (BTA) - Supports single data or burst transactions x Improved real-time support - Fast interrupt decode x Low-power operation - Active power management: powers down inactive units - Typical power 700mW @ 133MHz - Stand-by mode <300mW x Enhanced JTAG interface, for low-cost in-circuit emulation (ICE) x MIPS architecture ensures applications software compatibility throughout the RISController series of embedded processors x Industrial temperature range support x 3.3V operation (core and I/O)
x
Block Diagram
RISCore32300TM Extended MIPS 32 Integer CPU Core MMU RISCore4000 Compatible System Control w/ TLB Coprocessor (CPO)
Enhanced JTAG (ICE Interface)
8kB I-Cache, 2-set, lockable
2kB D-Cache, 2-set, lockable, write-back/write-through
Clock Generation Unit
RISCore32300 Internal Bus Interface
RC32364 Bus Interface Unit
The IDT logo is a registered trademark and ORION, RC4650, RC4640, RV4640, RC4600, RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
1 of 21
2000 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice
June 20, 2000
DSC 4510
79RC32364TM
Overview Device Overview
Targeted to a variety of performance-hungry, cost-sensitive embedded applications, the RC32364 is a new low-powered, low-cost member of the Integrated Device Technology, Inc. (IDT) RISController Series of Embedded Microprocessors. The RC32364 brings 64-bit performance levels to lower cost systems. High performance is achieved through the use of advanced techniques such as large on-chip two-way set-associative caches, a streamlined high-speed pipeline, high-bandwidth, and facilities such as early restart for data cache misses. Also, through IDT proprietary enhancements to the base MIPS architecture, the processor's performance, in particular applications, is further extended. The RC32364 is the first member of a new processor family that uses IDT's proprietary RISCore32300 CPU core. The RISCore32300 core continues IDT's tradition of high-performance through high-speed pipelines, high-bandwidth caches, and architectural extensions that serve the needs of specific markets; yet the RC32364 provides these capabilities in a low-cost, high-speed 32-bit enhanced MIPS architecture core, enabling a new level of price performance. Around the RISCore32300, the RC32364 integrates a fully RC5000 compatible memory management unit (MMU), substantial amounts of efficient cache memory, an enhanced debug capability, digital signal processing (DSP) extensions, and a low-cost system interface. The resulting device is well suited to the needs of mid-range communications equipment, xDSL equipment, and consumer devices. Also, being upwardly software compatible with the RC3000 family, the RC32364 will serve in many of the same applications as well as support applications that require integer DSP functions.
x
x x
x
MIPS IV prefetch operations, with various innovative hint subfields MIPS IV compatible conditional move instructions MAD, MUL and MSUB instructions added to the integer multiply units Two new instructions: Count Leading Ones (CLO) and Counts Leading Zeros (CLZ)
These integer unit enhancements combine to make the CPU well suited to applications that require high bandwidth, rapid computation, and/or DSP capability. The RISCore32300 register file has 32 general-purpose 32-bit registers that are used for scalar integer operations and address calculation. The register file consists of two read ports and two write ports and is fully bypassed to minimize operation latency in the pipeline. The RISCore32300 arithmetic logic unit (ALU) consists of the integer adder and logic unit. The adder performs address calculations in addition to arithmetic operations; the logic unit performs all of the logic and shift operations. Each unit is highly optimized and can perform an operation in a single pipeline cycle. The RC32364 uses a dedicated integer multiply/divide unit, optimized for high-speed multiply and multiply-accumulate operations. Table 1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued), latency (number of cycles until a result is available), and number of processor stalls (number of cycles that the CPU will always delay the pipeline) required for these operations. Each rate listed is expressed in terms of pipeline clocks.
Opcode MULT/U, MAD/U MSUB/U MUL Operand Size 16 bit 32 bit 16 bit 32 bit DIV, DIVU any Latency 3 4 3 4 36 Repeat 2 3 2 3 36 Stall 0 0 1 2 0
Device Performance
RC32364 is rated at 175 dhrystone MIPS at 133MHz. The internal cache bandwidth is over 1.2 GB/sec, with external bus bandwidth of 260MB/sec. Computational performance is further enhanced by the device's DSP capability, which supports 66 Million multiply-accummulate (MAC) operations per second at 133MHz. The RISCore32300 uses a 5-stage pipeline, similar to the RISCore3000 and the RISCore4000 processor families. The simplicity of the pipeline enables the processor to achieve high frequency while minimizing device complexity, reducing both cost and power consumption. Because this pipeline is not sensitive to the data conflicts that slowdown super-scalar machines, an added benefit to this pipeline approach is that sustained actual performance is much closer to the theoretical maximum performance. The RISCore32300 integer execution unit implements the MIPS 32 ISA. The RISCore32300 thus implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The 32-bit register resources include 32 general-purpose orthogonal integer registers, the HI/LO result register for the integer multiply/divide unit, and the program counter. RISCore32300 CPU core features include:
Table 1 RISCore32300 Integer Multiply/Divide Unit Operation Frequency
The original MIPS architecture defines that the results of a multiply or divide operation are placed in the HI and LO registers. Using the move-from-HI (MFHI) and move-from-LO (MFLO) instructions, these values can then be transferred to the general purpose register file. As an enhancement to the original MIPS ISA, the RC32364 implements an additional multiply instruction, MUL, which specifies that multiply results bypass the LO register and be placed immediately into the primary register file. By avoiding the explicit MFLO instruction, required when using LO, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased.
2 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM
Two atomic operations--multiply-add (MAD) and multiply-subtract (MSUB)--are used to perform the multiply-accumulate and multiplysubtract operations. The MAD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MAD and MSUB operations are used in numerous DSP algorithms and allow the RC32364 to cost reduce systems requiring a mix of DSP and control functions. Finally, for these operations, aggressive implementation techniques feature low latency along with pipelining to allow the issuance of new operations before a previous operation has been completed. The RC32364 also performs automatic operand size detection and implements hardware interlocks to prevent overrun, achieving high-performance with simple programming.
Operation Modes
The RC32364 supports two modes of operation: user mode and kernel mode. User mode is most often used for applications programs, and the kernel mode is typically used for handling exceptions and operating system kernel functions, including CP0 management and I/O device access. The processor enters kernel mode at reset and when an exception is recognized. While in kernel mode, software has access to the entire address space as well as all of the CP0 registers. User mode accesses are limited to a subset of the virtual address space and can be inhibited from accessing CP0 functions.
Virtual-to-Physical Address Mapping
The RC32364's 4GB virtual address space is divided into addresses that are accessible in either kernel or user mode (kuseg) and those that are accessible only in kernel mode (kseg2:0). Bits in a status register determine which virtual addressing mode will be used. While in user mode, the RC32364 provides a single, uniform 2GB virtual address space for the user's program. While operating in kernel mode, four distinct virtual address spaces, totalling 4GB, are simultaneously available and are differentiated by the high-order bits of the virtual address. The RC32364 reserves a small portion of the kernel address space for on-chip resources. These resources include those used by the Enhanced JTAG unit as well as registers used to configure the system bus interface. For fast virtual-to-physical address decoding, the RC32364 uses a fully associative translation lookaside buffer (TLB) that maps 32 virtual pages to their corresponding physical addresses. The TLB is organized as 16 pairs of even/odd entries mapping pages of sizes that vary from 4kBytes to 16 MBytes into the 4GB physical address space. To assist in controlling both the amount of mapped space and the replacement characteristics of various memory regions, the RC32364 provides two mechanisms. First, the page size can be configured, on a per entry basis, to map a page size of 4kB to 16MB (in multiples of 4). A CP0 register is loaded with the mapping page size which is then entered into the TLB when a new entry is written. Thus, operating systems can provide special purpose maps; for example, a typical frame buffer can be memory mapped with only one TLB entry. The second mechanism controls the replacement algorithm, when a TLB miss occurs. To select a TLB entry to be written with a new mapping, the RC32364 provides a random replacement algorithm; however, the processor provides a mechanism whereby a system specific number of mappings can be locked into the TLB and thus avoid being randomly replaced. This facilitates the design of real-time systems, by allowing deterministic access to critical software. The RC32364's TLB also contains information to control the cache coherency protocol for each page. Specifically, each page has attribute bits to determine whether the coherency algorithm is uncached, noncoherent write-back, or non-coherent write-through no write-allocate.
System Control Coprocessor (CP0)
In the MIPS architecture, the system control co-processor is responsible for the virtual-to-physical address translation and cache protocols, the exception control system, and the processor's diagnostics capability. Also, the system control co-processor (and thus the kernel software) is implementation dependent. Although the RISCore32300 implements a 32-bit ISA, the Memory Management Unit (MMU) that the RC32364 incorporates is modeled after the MMU found in the 64-bit RC5000 family and offers variable page size, enhanced cache write algorithm support, mapping of a larger portion of the virtual address space and a variable number of locked entries, relative to the traditional 32-bit R3000 style MMU. The RC32364's translation lookaside buffer (TLB) contains 16 entries, mapping a total of 32 pages or as much as 512 MB of memory at a time. The exception model that is implemented in the RC32364 is also consistent with that of the RC5000 family, including the treatment of kernel mode and exception processing. The RC32364 incorporates all system control co-processor (CP0) registers on-chip. These registers provide the path through which the virtual memory system's address translation is controlled, exceptions are handled, and operating modes are selected (for example, kernel vs. user mode, interrupts enabled or disabled, and cache features). In addition, the RC32364 includes registers to implement a real-time cycle counting facility, which aids in cache diagnostic testing, assists in data error detection, and facilitates software debug. Alternatively, this timer can be used as the operating system reference timer and can signal a periodic interrupt.
3 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM
This allows the system architect to allocate address space according to the most efficient use of bus bandwidth. For example, stack data may be accessed always as write-back, while packet data may be best accessed as write through, for later DMA out to an I/O port. The RC32364 cache controller works in conjunction with these attributes, enabling an application to alias a region of physical memory through multiple virtual spaces. The cache controller will also ensure that regardless of which address space is used the current copy of data will be provided when referenced, and it will further guarantee that the cache is properly managed with respect to main memory.
Cache Memory
To keep the RC32364's high-performance pipeline full and operating efficiently, the RC32364 incorporates on-chip instruction and data caches that can each be accessed in a single processor cycle. Each cache has its own 32-bit data path and can be accessed in the same pipeline clock cycle. The RC32364 incorporates a two-way set associative on-chip Instruction Cache. This virtually indexed, physically tagged cache is 8kB in size and parity protected. Because this cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access. The tag holds a 21-bit physical address, a valid bit, lock bit, a parity bit, and the FIFO replacement bit. For fast, single cycle data access, the RC32364 includes a 2kB onchip data cache that is two-way set associative with a fixed 16-byte (four words) line size. The data cache is protected with byte parity and its tag is protected with a single parity bit. It is virtually indexed and physically tagged to allow simultaneous address translation and data cache access. The RC32364 supports a cache-locking feature to critical sections of code and data into on-chip caches, to guarantee fast accesses. The implementation of cache-locking is on a "per-line" basis, enabling the system designer to maximize the efficiency of the system cache. Writes to external memory--whether cache miss write-backs or stores to uncached or write-through addresses--use the on-chip write buffer. The write buffer holds a maximum of four address and data pairs. The entire buffer is used for a data cache writeback and allows the processor to proceed in parallel with a memory update.
Debug Support
To facilitate software debug, the RC32364 adds a pair of watch registers to CP0. When enabled, these registers will cause the CPU to take an exception when a "watched" address is appropriately accessed. In addition, the RC32364 implements an Enhanced JTAG interface, which requires the inclusion of significant amounts of debug support logic on-chip, facilitating the development of low-cost in-circuit emulation equipment. For low-cost In-Circuit Emulation, the RC32364 provides an Enhanced JTAG interface. This interface consists of two modes of operation: Run-Time Mode and Real-Time Mode. The Run-Time Mode provides a standard JTAG interface for on-chip debugging, and the Real-Time Mode provides additional status pins-- PCST[2:0]--which are used in conjunction with JTAG pins for Real-Time Trace information at the processor internal clock or any division of the pipeline clock. The RC32364 implements the traditional RC4000 model of interrupt processing. However, this model has been enhanced to benefit realtime systems. To speed interrupt exception decoding, the RC32364 adds a separate interrupt vector. Unlike the RC3000 family--which utilizes a single common exception vector for all exception types (including interrupts)-- the RC32364 allows kernel software to enable a separate interrupt exception vector. When enabled, this vector location speeds interrupt processing by allowing software to avoid decoding interrupts from general purpose exceptions.
System interfaces
The RC32364 supports a 32-bit system interface, allowing the CPU to interface with a lower cost memory system. The main features of the system interface include: x Multiplexed address and data bus with Address Latch Enable (ALE) signal to demultiplex the A/D bus. x Support of variable port widths, including boot device. x Support of multiple pipeline to system clock ratios, with the CPU core frequency being derived from the input system clock. x Incorporation of a DMA arbiter, allowing an external master control of the external bus. The 32-bit system address/data (A/D) bus is used to transfer addresses and data between the RC32364 and the rest of the system. The ALE signal is provided to demultiplex the address from this bus. The DATAEN* signal indicates the data phase of the A/D bus and DT/R* indicates the direction of data flow. BE*[3:0] indicates the valid bytes on the bus. Additional ADDR[3:2] provides incremental address during burst transfers. To indicate system interface bus activity, the RC32364 provides a cycle-in-progress (CIP*) signal. The RD* and WR* signals indicate the type of cycle in progress. And to terminate cycle in progress, the
Development Tools
An array of tools facilitate rapid development of RC32364-based systems, allowing a wide variety of customers to take advantage of the processor's high-performance capabilities while maintaining short timeto-market goals. The RC32364 incorporates an enhanced JTAG debug interface. This interface uses a small number of pins, combined with on-chip debug support logic, to enable the development of low-cost in-circuit emulators for high-speed IDT processors.
4 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM
RC32364 also provides Ack*, Retry*, and BusErr* signals. This device also provides I/D* signals, to indicate whether instructions or data is being transferred. The Last* signal is provided to indicate that the last data transfer is in progress. The RC32364 provides six external interrupt signals: INT*[5:0] and a non-maskable interrupt (NMI*) signal. To share the system interface bus, the RC32364 provides BusReq* and BusGnt* signals to interface external DMA masters. To allow the external master control of the external bus, a DMA arbiter is provided. The RC32364 supports a variable bus width interface, enabling the CPU to operate with a mix of 8-bit, 16-bit, and 32-bit wide memories. To indicate the width of the memory or I/O space being accessed, the RC32364 provides two output signals, Width[1:0]. The width of various address spaces is programmed using the Port Width Control Register. The RC32364's physical memory is divided into several regions, and each region's width can be programmed by using this register. Within these regions, the bus turnaround time can also be programmed. Thus, the RC32364 can be simply mated with low-cost external memory subsystems. The large on-chip caches and the early restart serve to allow the processor to achieve high-performance even with such low-cost memory. The RISCore32300 offers a number of features relevant to lowpower systems, including low-power design, active power management and power-down modes of operation. The RISCore32300 is a static design. The RC32364 supports a WAIT instruction which is designed to signal the rest of the chip that execution and clocking should be halted, reducing system power consumption during idle periods.
Typical values for CA at various airflows are shown in Table 2 Note that the RC32364 implements advanced power management, which substantially reduces the average power dissipation of the device. CA
Airflow (ft/min) 144 TQFP 0 27 200 22 400 20 600 17 800 15 1000 14
Table 2 Thermal Resistance (CA) at Various Airflows
History Revision Histor y
August 1999: Changed references from MIPS-II to MIPS 32. Changed references from MIPS-IV to MIPS 64. Changed values in Clock Parameters Table, System Interface Parameters Table, and Power Consumption Table. Deleted Several Timing Diagrams. Added JTAG TIming Diagram. Jan. 12, 2000: Corrected information regarding the TRST* signal in Table 3. TRST* requires an external pull-down on the board. April 4, 2000: Adjusted values for DCLK in the System Interface Parameters table. Added Power Curves. June 20, 2000: Changed times for the Data Output Hold, TDO Output Delay Time, and TPC Output Delay Time parameters in the System Interface Parameters table. Revised values for PCST Output Delay Time in System Interface Parameters table.
Thermal Considerations
The RC32364 is a low-power CPU, consuming approximately 0.9W peak power. Thus, no special packaging considerations are required. The RC32364 is guaranteed in a case temperature range of 0 to +85 C, for commercial temperature devices; - 40 to +85 for industrial temperature devices. The type of package, speed (power) of the device, and airflow conditions affect the equivalent ambient temperature conditions that will meet this specification. The equivalent allowable ambient temperature, TA, can be calculated using the thermal resistance from case to ambient (CA) of the given package. The following equation relates ambient and case temperatures: TA = TC - P * CA where P is the maximum power consumption at hot temperature, calculated by using the maximum ICC specification for the device.
5 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM
RC32364 Clock RC32134 CPU I/F Serial PIO Timers, UART, Interrupt Ctl DMA Channels DRAM Ctl Memory & I/O Ctl Address & Control Memory & I/O SDRAM 32-bit Data Bus
PCI Bridge with Arbiter 32-bit, 33Mhz PCI Bus
Figure 1 System Block Diagram
Pin Description Table
The following is a list of the system interface pins available on the RC32364. Pin names ending with an asterisk (*) are active when low.
Pin System Interface AD(31:4) AD(3:0) I/O I/O Addr(31:4)/Data(31:4) High-order multiplexed address and data bits. Regardless of system byte ordering, AD(31) is the MSB of the address. Size(3:0)/Data(3:0) Valid sizes for the RC32364 are as follows: Size(3) 0 0 0 0 0 0 0 0 0 1 Size(2) 0 0 1 1 0 Size(1) 0 1 0 1 0 Size(0) Transfer Width 16 bytes 1 byte 2 bytes 3 bytes 4 bytes Type Description
Other encodings allow future generations to service other transfer sizes. During the data phase, AD[3:0] represents the Data(3:0). Addr(3:2) O Addr(3:2) Non-multiplexed address lines. These serve as the word within block address for cache refills (Addr(3:2)). The word within block address bits count in a sub-block ordering. Address Latch Enable. This signal provides set-up and hold times around the address phase of the AD bus. Address Strobe This active-low signal indicates valid address and the start of a new bus transaction. The processor asserts ADS* for the entire address cycle. This is the inverse of the ALE signal. Table 3 System Interface Pin Descriptions (Page 1 of 4)
ALE ADS*
O O
6 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM Pin Width(1:0) Type O Description Bus Width Indicates the Physical Memory/IO data bus size as follows: Width(1) 0 0 1 1 Width(0) 0 1 0 1 Port Width 8 bits 16 bits 32 bits Reserved
BE*(3:0)
O
ByteEnables(3:0)/Addr(1:0) Indicates which byte lanes are expected to participate in the transfer. Byte Lanes Enabled In Data Transfer Port Width 32-bit 16-bit 8-bit BE(3) Used Byte High Enable Not Used (Driven High) BE(2) Used Not Used Not Used (Driven High) BE(1) Used Address Bit 1 (A1) Address Bit 1 (A1) BE(0) Used Byte Low Enable Address Bit 0 (A0)
CIP* I/D* Rd* Wr* DataEn*
O O O O O
Cycle-in-progress Denotes that a cycle is in progress. Asserted in the address phase and continue asserted until the ACK* for the last data is sampled. I/D* Indicates that the current cycle is for an instruction (active high) or data (active low) transaction. Read This active-low signal indicates that the current transaction is a read. Write This active-low signal indicates that the current cycle transaction is a write. Data Enable This active-low signal indicates that the AD bus is in data cycle. DEN* is asserted after the address cycle (starting of data cycle), and deasserted at the end of the last data cycle. Data Transmit/Receive This active-low signal indicates the current cycle transaction of data direction. "High" is for a write cycle and "Low" is for a read cycle. Acknowledge Receiving Data On read transactions, this signal indicates to the RC32364 that the memory system has placed valid data on the A/D bus, and that the processor may move the data into the on-chip Read Buffer. On a write transaction, this indicates to the RC32364 that the memory system has accepted the data on the A/D bus. Last Data This active-low output is used to indicate the last data phase of a transfer.
DT/R* Ack*
O I
Last*
O
Handshake Interface BusErr* I Bus Error Indicates that a bus error has occurred. Table 3 System Interface Pin Descriptions (Page 2 of 4)
7 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM Pin Retry* I Type Description Retry Indicates that the current bus cycle must be terminated. Retry* is ignored after acceptance of the first data during a read cycle. During a write, Retry* is recognized in all data cycles.
Initialization Interface ColdReset* Reset* DMA Interface BusReq* I Bus Request This active-low signal is an input to the processor that is used to request mastership of the external interface bus. Mastership is granted according to the assertion of this input, taken back based on its negation. Bus Grant/ModeBit(5) This active-low signal is an output from the processor and is used to indicate that the CPU has relinquished mastership of the external interface bus. BusGnt* goes low initially for at least 2 clocks to indicate that the CPU has relinquished mastership of the external interface bus. After going low, BusGnt* returns high, either when the CPU makes an internal request for the bus or after BusReq* is de-asserted.During the power-on reset (Cold Reset), BusGnt* is an input, ModeBit(5). I I ColdReset This active-low signal is used for power-on reset. Reset This active-low signal is used for both power-on and warm reset.
BusGnt*
I/O
Interrupt Interface NMI* Int*(5:0) I I Non-Maskable Interrupt NMI is falling edge sensitive and an asynchronous signal. Interrupt/ModeBit(9:6) These interrupt inputs are active low to the CPU. During power-on, Int*(3:0) serves as ModeBit(9:6).
Debug Emulator Interface TCK I Testclock An input test clock, used to shift into or out of the Boundary-Scan register cells. TCK is independent of the system and the processor clock with nominal 50% duty cycle. TDI/DINT* On the rising edge of TCK, serial input data are shifted into either the Instruction or Data register, depending on the TAP controller state. During Real Mode, this input is used as an interrupt line to stop the debug unit from Real Time mode and return the debug unit back to Run Time Mode (standard JTAG). Requires an external pull-up on the board. TDO/TPC The TDO is serial data shifted out from instruction or data register on the falling edge of TCK. When no data is shifted out, the TDO is tri-stated. During Real Time Mode, this signal provides a non-sequential program counter at the processor clock or at a division of processor clock. TMS The logic signal received at the TMS input is decoded by the TAP controller to control test operation. TMS is sampled on the rising edge of the TCK. Requires an external pull-up on the board. TRST* The TRST* pin is an active-low signal for asynchronous reset of the debug unit, independent of the processor logic. Requires an external pull-down on the board. DCLK Processor Clock. During Real Time Mode, this signal is used to capture address and data from the TDO signal at the processor clock speed or any division of the internal pipeline. Table 3 System Interface Pin Descriptions (Page 3 of 4)
TDI/DINT*
I
TDO/TPC
O
TMS
I
TRST*
I
DCLK
O
8 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM Pin PCST(2:0) Type I/O Description PCST(2:0)/ModeBit(2:0) PC Trace Status Information 111 (STL) Pipe line Stall 110 (JMP) Branch/Jump forms with PC output 101 (BRT) Branch/Jump forms with no PC output 100 (EXP) Exception generated with an exception vector code output 011 (SEQ) Sequential performance 010 (TST) Trace is outputted at pipeline stall time 001 (TSQ) Trace trigger output at performance time 000 (DBM) Run Debug Mode During power-on reset (cold reset), PCST(2:0) serves as ModeBit(2:0). PCST(4:3)/ModeBit(4:3) PC Trace Status Information. Reserved Pins for future expansion. During power-on reset, PCST(4:3) serves as ModeBit(4:3). DebugBoot The Debug Boot input is used during reset and forces the CPU core to take a debug exception at the end of the reset sequence instead of a reset exception. This enables the CPU to boot from the ICE probe without having the external memory working. This input signal is level sensitive and is not latched internally. This signal will also set the JtagBrk bit in the JTAG_Control_Register[12].
PCST(4:3) DebugBoot
I/O I
Clock/Control Interface MasterClk VccP VssP Vcc I/O Vcc Core Vss I I I I I I MasterClock This input clock is the bus clock. The core frequency is derived by multiplying this clock up. VccP Quiet Vcc for PLL. VssP Quiet Vss for PLL. Supply voltage for output buffers. Supply voltage for internal logic. Ground. Table 3 System Interface Pin Descriptions (Page 4 of 4)
9 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM
Logic Diagram
Figure 2 illustrates the direction and functional groupings for the processor signals of the RC32364.
Clock/Control Interface
MasterClk VCCP VSSP
28 4 2
AD(31:4) AD(3:0) Addr(3:2) ALE ADS* Width(1:0) BE(3:0)* CIP* I/D*
TCK TDI/DINT* Debug Emulator Interface TDO/TPC TMS TRST* DCLK PCST(2:0) PCST(4:3) DebugBoot
3 2
4
RC32364 Logic Symbol
Rd* Wr* DataEn* DT/R* Ack* Last* ColdReset* Reset*
Handshake Signals
Bus Err* Retry*
6
Int*(5:0)
Vcc I/O Vcc Core Vss BusReq* BusGnt* DMA Interface
June 20, 2000
Figure 2 Logic Diagram for RC32364
10 of 21
*Notice: The information in this document is subject to change without notice
Interrupt Interface
NMI*
Initialization Interface
System Interface
2
79RC32364TM
RC32364 144-pin TQFP Package Pin-Out
Note that the asterisk (*) identifies an active-low pin. For maximum flexibility and future design compatibility, N.C. pins should be left floating.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Function Vcc I/O Vss TRST* TDO/TPC* TMS Vcc I/O Vss TCK TDI/DINT* DebugBoot PCST4 Vcc Core Vss PCST3 NMI* INT0* PCST2 Vcc I/O Vss DClk INT1* Vcc Core INT2* Reset* Vcc Core Vss Wr* Rd* PCST1 INT3* Vcc I/O Vss INT4* PCST0 INT5* NC Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 NC NC NC NC Addr3 Vcc I/O Vss AD10 ADDR2 BusReq* AD11 Vcc I/O Vss AD20 BE3 ColdReset* BusGNT* AD12 Vcc Core Vss AD19 BE2 Width1 AD13 Vcc I/O Vss AD18 BE1 Width0 AD14 Vcc I/O Vss AD17 BE0 NC NC Function Pin 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 NC NC NC ADS* AD16 Vss Vcc I/O AD15 I/D* VssP VccP NC NC NC NC MasterClk Vss Vcc I/O AD31 AD0 Ack* ALE Vss Vcc Core AD30 AD1 Vcc Core BusErr* Retry* AD29 Vss Vcc I/O AD2 Last* NC NC Function Pin 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 NC CIP* AD28 Vss Vcc I/O AD3 AD27 DataEn* AD4 Vss Vcc I/O AD26 AD5 DT/R* AD25 Vss Vcc Core AD6 AD24 AD7 AD23 Vss Vcc I/O AD8 Vss AD22 AD9 Vss Vcc I/O AD21 NC NC NC Vss NC NC Function
11 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM
Absolute Maximum Ratings
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Symbol VTERM TC TBIAS TSTG IIN IOUT Rating Terminal Voltage with respect to GND Operating Temperature(case) Case Temperature Under Bias Storage Temperature DC Input Current DC Output Current RC32364 3.3V5% Commercial -0.51 to 4.0 0 to +85 -55 to +125 -55 to +125 202 503 RC32364 3.3V5% Industrial -0.51 to 4.0 -40 to +85 -55 to +125 -55 to +125 202 503 V C C C mA mA Unit
1. VIN minimum = -2.0V for pulse width less than 15ns. VIN should not exceed VCC +0.5 Volts. 2. When VIN < 0V or VIN > VCC 3.
Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
Voltage Recommended Operation Temperature and Supply Voltage
Grade Commercial Industrial Temperature 0C to +85C (Case) -40C + 85C (Case) Gnd 0V 0V RC32364 VCC Core & Vcc I/O 3.3V5% 3.3V5%
AC Electrical Characteristics -- Commercial/Industrial Temperature Ranges--RC32364
VCC Core & VCC I/O = 3.3V 5%; TCase = 0C to +85C Commercial, TCase = -40 C to +85C Industrial
Clock Parameters--RC32364
Note: Operation of the RC32364 is only guaranteed with the Phase Lock Loop enabled
Parameter Pipeline clock frequency MasterClock HIGH MasterClock LOW MasterClock Frequency MasterClock Period Clock Jitter for MasterClock1 MasterClock Rise Time2 MasterClock Fall Time2 JTAG Clock Period JTAG Clock High and Low Time JTAG Clock Fall and Rise Time
1.
Symbol PClk tMCHIGH tMCLOW
--
Test Conditions
RC32364 100MHz Min 80 6 6 10 20 -- -- -- 100 40 -- Max 100 -- -- 50 100 250 3 3 -- -- 3
RC32364 133MHz Min 80 5 5 10 15 -- -- -- 100 40 -- Max 133 -- -- 67 100 250 3 3 -- -- 3
Units MHz ns ns MHz ns ps ns ns ns ns ns
Transition 2ns Transition 2ns -- -- -- -- -- -- -- --
tMCP tJitterIn1 tMCRise tMCFall tTCK tTCKLOW, tTCKHIGH tTCKFall, tTCKRise
Guaranteed by design Fall times are measured between 10% and 90%.
2. Rise and
12 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM
System Interface Parameters--RC32364
Parameter Data Output Data Output Hold Data Output for ALE Data Setup Symbol
tDO = Max
Test Conditions
RC32364 100MHz Min -- 0.7 -- Max 6 -- 6 -- -- -- -- -- -- 3.5 6 -- -- 6 6 -- --
RC32364 133MHz Min -- 0.7 -- 3 5 0.5 100 12.5 2.5 -- -- 4 2 -1 -1 100 3 Max 6 -- 6 -- -- -- -- -- -- 3.5 6 -- -- 6 6 -- --
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tDOH tDOA tDS tDH tTCK, t3 tDCK, t11 tDCK High, t9 tDCK Low, t10 tDCK Rise, t15 tDCK Fall, t15 tTDODO, t4 tTDIS, t5 tTDIH, t6 tTPCDO, t8 tPCSTDO, t7 tTRSTLow, t12 tTRSTR, t13 trise = 2ns tfall = 2ns
3 6 0.5 100 12.5 2.5 -- -- 4 2 -1 -1 100 3
Data Setup Special: Ack, Retry, BusErr tDSS Data Hold JTAG Clock Period DCLK Clock Period DCLK High, Low Time DCLK Rise, Fall Time TDO Output Delay Time TDI Input Setup Time TDI Input Hold Time TPC Output Delay Time PCST Output Delay Time TRST* Low TIme TRST* Removal TIme
DC Electrical Characteristics -- Commercial/Industrial Temperature Ranges--RC32364
VCC Core & VCC I/O = 3.3V 5%; TCase = 0C to +85C Commercial, TCase = -40 C to +85C Industrial
Parameter Min VOL VOH VOL VOH VIL VIH CIN COUT I/OLEAK -- VCC - 0.1V -- 2.4V -0.5V 0.7VCC -- -- -- RC32364 100MHz Max 0.1V -- 0.4V -- 0.2VCC VCC +0.3V 10pF 10pF 20uA Min -- VCC - 0.1V -- 2.4V -0.5V 0.7VCC -- -- -- RC32364 133MHz Max 0.1V -- 0.4V -- 0.2VCC VCC + 0.3V 10pF 10pF 20uA -- -- -- -- Input/Output Leakage |IOUT|= 4mA |IOUT|= 20uA Conditions
13 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM
Output Loading For AC Testing
VREF
+1.5V
- + CLD
To Device Under Test
Figure 3 Output Loading for AC Testing
Signal All Signals 50 pF
Cld
Power Consumption -- RC32364
Parameter System Condition: ICC standby1 RC32364 100MHz Typical 100/50MHz 50mA 90mA Maximum RC32364 133MHz Typical 133/67MHz 50mA 90mA Maximum -- CL = 50pF Tc = 25oC Vcc core & Vcc I/O = 3.65V CL = 50pF TC = 25oC Vcc core, Vcc I/O = 3.65V CL = 50pF TC = 25oC Vcc core, Vcc I/O = 3.65V Conditions
active
160mA
180mA
200mA
250mA
P
power 0.58W dissipation
Executing wait instruction
0.6W
0.7Watt
0.9
1.
Capacitive Load Deration -- RC32364
Parameter Load Derate Symbol CLD -- Test Conditions 100MHz Min -- Max 2 133MHz Min -- Max 2 Units ns/25pF
14 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM
Power Curves
The following two graphs contain power curves that show power consumption at various bus frequencies. Note: Only pipeline frequencies that are integer multiples (2x, 3x, etc.) of bus frequencies are supported.
275.0 225.0 ICC (mA) 175.0 8x 125.0 75.0 25.0 10 15 20 25 30 35 40 45 50 55 60 65 System Bus Speed (MHz)
Figure 4 Typical Power Usage - RC32364
3x 6x 5x 4x 7x
2x
2x 3x 4x 5x 6x 7x 8x
350.0 300.0 ICC (mA) 250.0 200.0 150.0 100.0 50.0 10 15 20 25 30 35 40 45 50 55 60 65 System Bus Speed (MHz)
Figure 5 Maximum Power Usage - RC32364
5x 6x 7x 8x 4x
3x 2x 2x 3x 4x 5x 6x 7x 8x
15 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM
Timing Characteristics -- RC32364
tMCKP tMCKHIGH tMCKLOW
MasterClock Input Output
tMCRISE tMCFALL
tDS tDH
tDO tDO
ALE Ack* Retry* BusErr*
tDOH tDOA tDSS tDH
Figure 6 System Clocks Data Setup, Output, and Hold timing
VCC MasterClock (MClk) ColdReset* Reset* ModeBit[9:0] >= 100 ms >= 10 ms >= 64 MClk cycles
Figure 7 Mode Configuration Interface Reset Sequence
16 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM
Standard JTAG Timing
Figure 8 represents the timing diagram for the EJTAG interface signals. The standard JTAG connector is a 10-pin connector providing 5 signal and 5 ground pins. For Enhanced JTAG, a 24-pin connector has been chosen providing 12 signal pins and 12 ground pins. This guarantees the elimination of noise problems by incorporating a signal-ground type arrangement.
TCK DCLK
t3 t14 t1 t14 t2 t15
TPC,PCST[2:0] capture t11 t15 t9 t10
TDI/DINT* TMS TDO/TPC, TPC[8:2] PCST[2:0], t7 TRST*
Notes to diagram: t1 = tTCKlow t2 = tTCKHIGH t3 = tTCK t4 = tTDODO t5 = tTDIS t6 = tTDIH t7 = tPCSTDO t8 = tTPCDO t9 = tDCKHIGH t10 = tDCKLOW
t5 TDO t4
t6 TDO t8
TPC
PCST
t13 t12
t11 = tDCK t12 = tTRSTDO t13 = tTRSTR t14 = tTCK RISE, tTCK FALL t15 = tDCK RISE, tDCK FALL
Figure 8 Standard JTAG timing
17 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM
Table 4 shows the pin numbering for the Standard EJTAG (EJT) connector. All the even numbered pins are connected to GROUND. The two righthand most columns show the target signal direction and the recommended termination at the target. Target termination resistors may be internal to the chip or external on the board.
PIN 1 3 5 7 9 11 13 15 17 19 21 23
1. The 2.
SIGNAL TRST* (optional) TDI/DINT* TDO/TPC TMS TCK RST* PCST[0] PCST[1] PCST[2] DCLK Debugboot VIO
TARGET I/O Input Input Output Input Input Input Output Output Output Output Input Input
TERMINATION1 10 k pull-down resistor 10 k pull-up resistor 33 series resistor 10 k pull-up resistor 10 k pull-up resistor2 10 k pull-up resistor 33 series 33 series 33 series 33 series 10 k pull-down resistor Must be connected to the VCC IO supply of the device.
Table 4 Pin Numbering of the JTAG and EJTAG Target Connector
value of the series resistor may depend on the actual PCB layout situation. TCK pull-up resistor is not required according to the JTAG (IEEE1149) standard. It is indicated here to prevent a floating CMOS input when the EJTAG connector is unconnected.
18 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM
RC32364 Package Drawing -- 144-pin TQFP
(Note: The RC32364 is available in a 144-pin thin quad flat pack (TQFP) package.)
19 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM
RC32364 Package Drawing
-- Page Two
20 of 21
*Notice: The information in this document is subject to change without notice
June 20, 2000
79RC32364TM
Ordering Information
IDT79RCXX Product Type YY Operating Voltage XXXX Device Type 999 Speed A Package A Temp range/ Process
Blank Commercial Temperature Range (0C to +85C Case)
I
Industrial Temperature Range (-40C to +85C Case)
DA
144-pin TQFP
100 133
100 MHz PClk 133 MHz PClk
364
Embedded Processor
V
3.3V +/-5%
79RC32 32-bit Embedded Microprocessor
Valid Combinations
IDT79RC32V364 - 100,133 DA IDT79RC32V364 - 100,133 DAI TQFP package, Commercial Temperature TQFP package, Industrial Temperature
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com
21 of 21
for Tech Support: email: rischelp@idt.com phone: 408-492-8208
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
June 20, 2000
*Notice: The information in this document is subject to change without notice

▲Up To Search▲

Price & Availability of 79RC32364

	To Download 79RC32364 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .